The present application relates to semiconductor device fabrication, and more particularly, to the fabrication of stacked vertical field effect transistors (FETs).
Complementary metal oxide semiconductor (CMOS) technology is employed in almost every electronic circuit application. CMOS circuits include both n-type FETs and p-type FETs. In a typical CMOS layout, a p-type FET and an n-type FET are serially connected, typically from source to drain or vice versa. As circuits are scaled to smaller dimensions and thus a smaller area, vertically stacking p-type FETs and n-type FETs is quite attractive to provide greater device packing density. However, in a conventional horizontal FET device configuration in which the source-drain current is following in a direction parallel to a substrate surface, vertically stacking multiple FETs is difficult and may involve bonding. In a vertical FET device configuration in which the source-drain current is following in a direction perpendicular to a substrate surface, stacking multiple FETs can be easier. Therefore, a processing scheme for effectively stacking vertical FETs remains needed.